In the fabrication of multi-layered printed wiring boards when an additional wiring plane is added to a circuitized substrate, an additional layer of dielectric is applied atop the existing circuitry on the substrate, and the additional circuitization is added atop the dielectric layer. To connect the circuitry atop the dielectric and the circuitry within the multi-layer, through holes and blind vias are drilled. Unfortunately, it is difficult to drill through holes and vias having a diameter smaller than about 10 mils. Thus such drilled through holes and vias consume real estate.
In an attempt to increase real estate, methods have been devised for forming smaller diameter through holes and blind vias. Laser drilling and laser ablation provide smaller diameter through holes and vias but they are time consuming and expensive.
Another method involves placing a photoimageable dielectric atop a substrate, photoimaging microvias, then plating circuitry atop the dielectric; however, it is typically difficult to get good adhesion of the circuitry to the dielectric; or where acceptable adhesion is obtained, it is achieved by roughening by chemical means, such as by a permanganate etch. Permanganate etchants are not desirable because they employ harsh chemical baths.
Another method has been developed, which involves laminating a dielectric layer having a metal layer atop, to a substrate, subtractive etching vias in the foil, then plasma etching out vias in the dielectric layer organic under foil. This is not only time consuming, but the line circuitry density is not satisfactory because small diameter vias are not achievable.
Accordingly, it would be desirable to have a method for adding additional wiring planes to substrates, which does not require mechanical drilling to form vias and through holes, and thus increases available real estate yet is efficient, does not require harsh etchants, and the circuitization in the additional wiring plane adheres to the dielectric layer.